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1999 micr o chi p technology inc. ds21166e - pag e 1 fe a tures ? s i ng l e su p ply wit h o p e r at i o n d o w n t o 2. 2 v ? low pow e r cmos t e c h n o l o g y - 1 m a ac t i v e curre n t typ i cal - 1 0 a st a nd b y c u rre n t t y p i c a l a t 5. 5 v - 5 a sta n d b y c u rren t typica l at 3 .0v ? or g a n i z e d a s a s i n g le b l o c k of 2 5 6 b y t e s ( 2 56 x 8 ) ? so f t w a re w r i t e p ro t e c t i on f o r low e r 1 2 8 by t e s ? ha r d w ar e w r it e pr o tecti o n f or e ntir e ar r a y ? 2 -wire se r i al in t er f a c e b u s , i 2 c? c o m p at i b le ? 1 00khz ( 2.2v ) an d 4 0 0khz ( 5 v) c o m p at i bi l ity ? se l f - t i m e d w r i t e c y c l e ( i n c l u d i n g a u t o - e r a s e ) ? p a ge-w r i t e b u f f e r f o r u p to 1 6 b ytes ? 3 .5 ms ty p ica l w r i te cyc l e t i m e f o r pa g e-w r i t e ? 1 ,00 0 ,0 0 0 e r a s e /writ e c y c l e s g u a r a n teed ? esd p rot e ct i o n >4 , 00 0 v ? da t a r e te n tio n > 2 0 0 y ears ? 8-pin di p , soic o r tssop pa c kages ? a v a i l a b l e f o r e xt e nd e d t e m p e r at u re r a ng e s description t h e m i c ro c h i p t e c h n o l o g y i n c. 2 4 l c s52 i s a 2k b i t e l ect r ical l y e r asa b l e p r om c a pa b l e o f op e r ati o n a cr o ss a bro a d v o l ta g e r a n g e (2. 2 v t o 5 . 5v) . th i s d e v i ce h a s a s o f t w a re w r i t e p ro t e ct f e a t u re f o r t h e low e r h a lf o f t he a r r a y , a s w e ll a s an e xt e r n a l p i n th a t c a n b e u se d to w r i te pr o tect t h e e n tir e a r r a y . t he sof t w are w r i te p rot e ct f e atur e i s en a b le d b y s en d in g t he d e v i ce a s p e- c i a l c o mman d , an d o n c e th i s f e at u re h a s b e en e n a b l e d, i t can n ot b e r e v e rs e d . in a dd i ti o n t o t h e soft w a re p ro- t e c t f e a t u r e , t h ere i s a w p p i n t h a t c a n b e u s ed t o w r i t e p rot e ct th e ent i re ar r a y , reg a rd l ess of wh e the r t h e s o ft- ware w r i t e pr o t e c t r e g i s t e r h a s b e e n w r i t t e n or n o t . t h is a ll o ws t h e s y s tem d e s i gn e r to p rot e c t no n e , h a l f or a l l o f t he ar r a y , de p en d i n g on t h e ap p li c at i o n . th e d e v i c e i s o rg a ni z e d a s a s i n g l e b l o c k o f 2 5 6 x 8 -bi t m e m o r y w i th a 2-wir e s e r ia l i n ter f ac e . l o w v ol t ag e d e si g n p er- mit s o p e r at i on d o wn t o 2. 2 v o l t s w i th t y p i c a l s t an d b y a nd act i v e curr e nts o f on l y 5 a an d 1 ma resp e ct i v e l y . t h e d e v i c e h a s a pa g e-writ e ca p a b il i ty f o r up t o 1 6 b y te s o f d a ta . t h e d e vi c e i s a v ai l a b l e i n t h e st a nd a r d 8- p in d i p , 8 -p i n soic a nd t ssop pa c ka g e s . - commercial (c): 0 c t o +70c - i n dust r i al ( i ): -4 0 c t o + 8 5c p a c k a ge t ypes block di a gram pdip/soic tssop a0 a1 a2 vss vcc wp scl s d a 2 4 lcs52 1 2 3 4 8 7 6 5 vcc wp scl s d a a0 a1 a2 vss 24l c s 52 1 2 3 4 8 7 6 5 i/o c o ntrol lo g ic m e m o r y co n tr o l l o gic xdec hv g e ner a tor st a nd a rd arr a y sof t w a r e w r i t e w r ite p r ot e ct ci r cuit r y ydec vcc vss s e n s e amp r/w c o nt r ol s d a s c l a0 a 1 a2 wp p r ot e cted a r ea ( 0 0 h -7 f h) 24lcs52 2k 2.2v i 2 c ? serial eep r om with softwa r e write p r otect i 2 c is a trad e m a r k o f philip s co r p orati o n.
24lcs52 ds21166e-page 2 1999 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc ...................................................................................7.0v all inputs and outputs w.r.t. v ss ............... -0.6v to v cc +1.0v storage temperature ..................................... -65c to +150c ambient temp. with power applied ................-65c to +125c soldering temperature of leads (10 seconds) ............. +300c esd protection on all pins............................................ ? 4 kv *notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin function table name function v ss sda scl v cc a0, a1, a2 wp ground serial address/data i/o serial clock +2.2v to 5.5v power supply chip selects hardware write protect table 1-2: dc characteristics figure 1-1: bus timing start/stop v cc = +2.2v to +5.5v commercial (c): tamb = 0c to +70c industrial (i): tamb = -40c to +85c parameter symbol min. max. units conditions scl and sda pins: high level input voltage v ih .7 v cc v low level input voltage v il .3 v cc v hysteresis of schmitt trigger inputs v hys .05 v cc v(note) low level output voltage v ol .40 v i ol = 3.0 ma, v cc = 2.5v input leakage current all i/o pins i li -10 10 a v in = 0.1v to 5.5v, wp = vss wp pin i li -10 50 a wp = v cc output leakage current i lo -10 10 a v out = 0.1v to 5.5v pin capacitance (all inputs/outputs) c in , c out 10pfv cc = 5.0v (note) tamb = 25c, f clk = 1 mhz operating current i cc write 3 ma v cc = 5.5v, scl = 400 khz i cc read 1 ma v cc = 5.5v, scl = 400 khz standby current i ccs 30av cc = 3.0v, sda = scl = v cc 100 a v cc = 5.5v, sda = scl = v cc wp = v ss , a0, a1, a2 = v ss note: this parameter is periodically sampled and not 100% tested. scl sda t su : sta t hd : sta v hys t su : sto start stop
1999 microchip technology inc. ds21166e-page 3 24lcs52 table 1-3: ac characteristics figure 1-2: bus timing data parameter symbol vcc = 2.2-5.5v std mode vcc = 4.5 - 5.5v fast mode units remarks min. max. min. max. clock frequency f clk 100 400 khz clock high time t high 4000 600 ns clock low time t low 4700 1300 ns sda and scl rise time t r 1000 300 ns (note 1) sda and scl fall time t f 300 300 ns (note 1) start condition hold time t hd : sta 4000 600 ns after this period the first clock pulse is generated start condition setup time t su : sta 4700 600 ns only relevant for repeated start condition data input hold time t hd : dat 0 0 ns (note 2) data input setup time t su : dat 250 100 ns stop condition setup time t su : sto 4000 600 ns output valid from clock t aa 3500 900 ns (note 2) bus free time t buf 4700 1300 ns time the bus must be free before a new transmission can start output fall time from v ih minimum to v il maximum t of 250 20 +0.1 cb 250 ns (note 1), cb e 100 pf input filter spike suppression (sda and scl pins) t sp 50 50 ns (note 3) write cycle time t wr 10 10 ms byte or page mode endurance 1m 1m cycles 25c, v cc = 5.0v, block mode (note 4) note 1: not 100% tested. cb = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a specific appli- cation, please consult the total endurance model which can be obtained on our website. scl sda sda t su : sta t f t low t high t r t hd : dat t su : dat t su : sto t hd : sta t buf t aa t aa t sp t hd : sta in out
24lcs52 ds21166e-page 4 1999 microchip technology inc. 2.0 functional description the 24lcs52 supports a bi-directional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions, while the 24lcs52 works as slave. both master and slave can operate as transmitter or receiver but the master device deter- mines which mode is activated. 3.0 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last six- teen will be stored when doing a write operation. when an overwrite does occur it will replace data in a first in first out fashion. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. 3.6 device addressing a control byte is the first byte received following the start condition from the master device. the first part of the control byte consists of a 4-bit control code which is set to 1010 for normal read and write operations and 0110 for writing to the write protect register. the control byte is followed by three chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24lcs52 devices on the same bus and are used to determine which device is accessed. the chip select bits in the control byte must correspond to the logic lev- els on the corresponding a2, a1 and a0 pins for the device to respond. the device will not acknowledge if you attempt a read command with the control code set to 0110. note: the 24lcs52 does not generate any acknowledge bits if an internal program- ming cycle is in progress. figure 3-1: data transfer sequence on the serial bus characteristics scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition
1999 microchip technology inc. ds21166e-page 5 24lcs52 the eighth bit of slave address determines if the master device wants to read or write to the 24lcs52 (figure 3- 2). when set to a one a read operation is selected and when set to a zero a write operation is selected. figure 3-2: control byte allocation 4.0 write operations 4.1 byte write following the start signal from the master, the device code(4 bits), the chip select bits (3 bits), and the r/w bit which is a logic low is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24lcs52. after receiving operation control code chip select r/w read write set write protect register 1010 1010 0110 a2 a1 a0 a2 a1 a0 a2 a1 a0 1 0 0 slave address r/w a 1 0 1 0 a2 a1 a0 start read/write 0 1 1 0 a2 a1 a0 or another acknowledge signal from the 24lcs52 the master device will transmit the data word to be written into the addressed memory location. the 24lcs52 acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the 24lcs52 will not generate acknowledge signals (figure 4-1). if an attempt is made to write to the array when the software or hard- ware write protection has been enabled, the device will acknowledge the command but no data will be written. the write cycle time must be observed even if the write protection is enabled. 4.2 page write the write control byte, word address and the first data byte are transmitted to the 24lcs52 in the same way as in a byte write. but instead of generating a stop con- dition, the master transmits up to 15 additional data bytes to the 24lcs52 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condi- tion. after the receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order four bits of the word address remains constant. if the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an inter- nal write cycle will begin (figure 4-2). if an attempt is made to write to the array when the hardware write pro- tection has been enabled, the device will acknowledge the command but no data will be written. the write cycle time must be observed even if the write protection is enabled. note: page write operations are limited to writing bytes within a single physical page, regard- less of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore neces- sary for the application software to prevent page write operations that would attempt to cross a page boundary.
24lcs52 ds21166e-page 6 1999 microchip technology inc. figure 4-1: byte write figure 4-2: page write s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k s p bus activity master sda line bus activity s t a r t control byte word address (n) data n data n + 15 s t o p a c k a c k a c k a c k a c k
24lcs52 ds21166e-page 7 1999 microchip technology inc. 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master send- ing a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for flow diagram. figure 5-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes 6.0 write protection the 24lcs52 has a software write protect feature that allows the lower half of the array (addresses 00h - 7fh) to be permanently write protected, as well as a wp pin that can be used to protect the entire array. 6.1 software write protect the software write protect feature is invoked by writing to the write protect register. this is done by sending a command similar to a normal write command. as shown in figure 6-1, the write protect register is written by sending a write command with the slave address set to 0110 instead of 1010 and the address bits and data bits are dont cares. once the software write protect register has been written, the device will not acknowl- edge the 0110 control byte. once the software write protect register has been written, the write protec- tion is enabled and cannot be reversed, even if the device is powered down. 6.2 hardware write protect the wp pin can be tied to vcc, v ss , or left floating. if tied to v cc , the entire array will be write protected, regardless of whether the software write protect regis- ter has been written or not. if the wp pin is set to v cc , it will prevent the software write protect register from being written. if the wp is tied to v ss or left floating, then write protection is determined by the status of the software write protect register. figure 6-1: setting write protect register s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k
24lcs52 ds21166e-page 8 1999 microchip technology inc. 7.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 7.1 current address read the 24lcs52 contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with the r/w bit set to one, the 24lcs52 issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24lcs52 discontinues transmission (figure 7-1). 7.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24lcs52 as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24lcs52 will then issue an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24lcs52 dis- continues transmission (figure 7-2). after this com- mand, the internal address counter will point to the address location following the one that was just read. 7.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the 24lcs52 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24lcs52 to transmit the next sequentially addressed 8-bit word (figure 7-3). to provide sequential reads the 24lcs52 contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 7.4 contiguous addressing across multiple devices the chip select bits a2, a1, a0 can be used to expand the contiguous address space for up to 16k bits by add- ing up to eight 24lcs52 devices on the same bus. in this case, software can use a0 of the control byte as address bit a8, a1 as address bit a9, and a2 as address bit a10. it is not possible to sequentially read across device boundaries. figure 7-1: current address read bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k
1999 microchip technology inc. ds21166e-page 9 24lcs52 figure 7-2: random read figure 7-3: sequential read s p s bus activity master sda line bus activity s t a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k p bus activity master sda line bus activity s t o p control byte a c k n o a c k data n data n + 1 data n + 2 data n + x a c k a c k a c k 8.0 pin descriptions 8.1 sda serial address/data input/output this is a bi-directional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pull-up resistor to v cc (typical 10k? for 100 khz, 2 k? for 400 khz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop condi- tions. 8.2 scl serial clock this input is used to synchronize the data transfer from and to the device. 8.3 a0, a1, a2 the levels on these inputs are compared with the cor- responding bits in the slave address. the chip is selected if the compare is true. up to eight 24lcs52 devices may be connected to the same bus by using different chip select bit combina- tions. these inputs must be connected to either vcc or vss. 8.4 wp this is the hardware write protect pin. it can be tied to v cc , v ss , or left floating. if tied to vcc, the hardware write protection is enabled. if the wp pin is tied to vss the hardware write protection is disabled. if the wp pin is left floating, an internal pull down resistor will pull the wp pin to vss and the hardware write protection will be disabled. 8.5 noise protection the 24lcs52 employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.
24lcs52 ds21166e-page 10 1999 microchip technology inc. notes:
24lcs52 1999 microchip technology inc. ds21166e-page 11 24lcs52 product identification system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory o r the listed sales offices. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead st = tssop, 8-lead temperature blank = 0 c to +70c range: i = C40c to +85c device: 24lcs52 2k i 2 c serial eeprom 24lcs52t 2k i 2 c serial eeprom (tape and reel) 24lcs52 /p
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8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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